The present invention relates to an input circuit of an IC (Integrated Circuit) for receiving data signals from outside the IC.
The input circuit is used for receiving data signals exchanged among different ICs by way of bus-lines, for example, and receives either a HIGH level signal or a LOW level signal when logical signals are exchanged among the ICs. The input circuit of an IC has an input terminal for receiving data signals from outside the IC and an output terminal for transferring the received signals inside the IC.
Concerning the logical signal exchange among ICs, signal levels are standardized so that the HIGH level or the LOW level of a signal may be discriminated commonly, and every signal is exchanged according to the standard. According to the TTL (Transistor Transistor Logic) interface standard, for example, the minimum voltage of the HIGH level signal to be exchanged (hereinafter abbreviated as the VOHMIN) is defined to be 2.4V and the maximum voltage of the LOW level signal to be exchanged (hereinafter abbreviated as the VOLMAX) is defined to be 0.4V.
However, the maximum voltage of the HIGH level signal to be exchanged (hereinafter abbreviated as the VOHMAX) or the minimum voltage of the LOW level signal to be exchanged (hereinafter abbreviated as the VOLMIN) is not defined in the TTL interface standard. Therefore, in almost every IC, a potential level near the maximum power supply voltage is used as the HIGH level signal and a potential level near the ground voltage is used as the LOW level signal. This situation is the same for ICs designed according to the conventional CMOS interface, that is, their VOHMAXs and the VOLMINs have been determined according to their power supply voltages and the ground voltages.
However, the power supply voltage of the ICs has been lowered along with progress of their fine integration, and hence, there have arisen cases where ICs of different power supply voltages (5V and 3V, for example) should be used in combination. In these cases, different power supply voltages must be supplied for each IC, so that circuit elements comprised in the IC of the lower power supply voltage may not be broken by a power supply voltage higher than their tolerance. As a consequence, data signals of two different VOHMAXs, one near 5V and the other near 3V, in the example, may be exchanged between the ICs, because the ICs are defined to be sufficient at least when their VOHMINs and the VOLMAXs are conformed to the standard such as defined in the above described TTL interface.
As above described, circuit elements of an IC designed to work with 3V may be broken when 5V is supplied as a power supply to the IC. In the same way, when data signals of the VOHMAX about 5V are received by an input circuit of an IC of 3V, elements of the input circuit may be broken when there is no countermeasure is taken.
Therefore, the input circuit of an IC designed to work with a low power supply voltage, 3V, for example, should be so configured that it can receive signals delivered from another IC working with a high power supply voltage, 5V, for example, without breaking its element.
FIG. 3 is a circuit diagram illustrating a conventional input circuit of an IC for receiving data signals of the VOHMAX higher than its power supply voltage.
In the input circuit of FIG. 3, an input terminal IN is connected to a base of a PNP transistor 301. An emitter of the PNP transistor 301 is connected to a ground terminal VSS and a collector thereof is connected to a power supply VDD through a resistance element 308. The collector of the PNP transistor 308 is coupled to gates of a pMOS transistor 311 and an nMOS transistor 312. A source of the pMOS transistor 311 is connected to the power supply VDD and a drain thereof is coupled to an output terminal OUT and a drain of the nMOS transistor 312, whereof a source is connected to the ground terminal VSS.
In a case where a power supply voltage, 3V, for example, is supplied between the power supply terminal VDD and the ground terminal VSS, and a HIGH level signal, 5V, for example, higher than the power supply voltage is impressed to the input terminal IN from another IC working with 5V supply.
In this case, the base-emitter voltage of the PNP transistor 301 becomes backward-biased, and the PNP transistor 301 is made OFF. Hence, the emitter of the PNP transistor 301 is cut from the potential of the input terminal IN, and the gates of the pMOS transistor 311 and the nMOS transistor 312, which compose a CMOS inverter, are supplied with the power supply voltage of 3V through the resistance element 308. Thus, degradation of the gate oxidation film, which may occur when the gates of the pMOS transistor 311 and the nMOS transistor 312 are connected directly to the input terminal IN, is prevented.
The pMOS transistor 311 being made OFF and the nMOS transistor 312 being made ON in the CMOS inverter, potential of the output terminal OUT is shifted to the ground voltage in this case, which is transferred to inner circuits of the IC as the LOW level signal indicating inverse logic of the signal received through the input terminal IN.
When a LOW level signal near the ground voltage is impressed to the input terminal IN, it is supplied to the base of the PNP transistor 301 whereof the emitter is supplied with the power supply voltage of 3V through the resistance element 308. Hence, the base-emitter voltage being forward-biased, the PNP transistor 301 becomes ON, and gate potential of the CMOS inverter is lowered near the ground voltage. The pMOS transistor 311 made ON and the nMOS transistor 312 made OFF, the potential of the output terminal OUT is shifted to the power supply voltage of 3V in this case, which is transferred to the inner circuits as the HIGH level signal indicating inverse logic of the signal received through the input terminal IN.
Also in this case, there is no problem in the degradation of gate oxidation film, which may occur when a VOLMIN too much lower than the ground voltage is impressed directly to the gates of the CMOS inverter.
As to the PNP transistor 301, a lateral type PNP transistor is used, wherein high endurance, about 10 to 20V, can be obtained against the base-emitter and the base-collector voltage difference. The lateral type PNP transistor has also merit in that it can be easily configured on an IC chip with ordinary CMOS or BiCMOS fabrication processes.
As described, above the problem of the degradation of gate oxidation film of the pMOS transistor 311 and the nMOS transistor 312 is prevented in the conventional input circuit of FIG. 3 even when a HIGH level signal higher than the power supply voltage is supplied to the input terminal IN, by providing the PNP transistor 301 having the base connected to the inpit terminal IN and the emitter supplied with the power supply voltage through the resistance element 308 and connected to the gates of the pMOS transistor 311 and the nMOS transistor 312.
However, in the conventional input circuit of FIG. 3, there is a problem of a current flowing through the base of the PNP transistor 310, as will be described i the following paragraphs.
When a LOW level signal near the ground voltage is run into the input terminal IN, the PNP transistor 301 is made ON. The resistance value of the resistance element 308 is generally set to be about 1 to 10K.OMEGA. to ensure high-speed switching of the CMOS inverter. Therefore, the emitter current of the PNP transistor 301 becomes about 0.3 to 3 mA, when the power supply voltage is 3V.
A part of the emitter current flows out through the base of the PNP transistor 310, as the base-emitter voltage is forward-biased when the LOW level signal is impressed there. The forward current-gain of the lateral type transistor is generally small and often shows a value smaller than 10 times, even one time when fabrication processes are not sufficiently controlled. When the forward current-gain is one time, it means the same current flows out through the base with the current flowing through the collector, that is, a half of the emitter current of the PNP transistor 301.
In the input circuit for receiving external signals, its input terminal may be left open receiving neither of the HIGH level signal nor the LOW level signal. When the input terminal is left open, the logical level of the input terminal becomes unstable. Therefore, there is usually provided a resistance element (hereinafter called the pull-up resistor) connected between the input terminal and the power supply terminal (hereinafter called the pull-down resistor) or connected between the input terminal and the ground terminal, for defining the logical level of the input terminal either to the HIGH level or the LOW level. In the input circuit in which it is possible to receive a HIGH level signal higher than the power supply voltage, the high voltage of the input signal may leak to the inner circuit by way of the power supply terminal, in case the pull-up resistor is provided. Therefore, the pull-down resistor is usually provided, such as a pull-down resistor RPD of the input circuit of FIG. 3 connected between the input terminal IN and the ground terminal VSS. As to the pull-down resistor, comparatively high resistance value about 10 to 50K.OMEGA. is selected, for retaining sufficient input impedance.
When output impedance of the external LOW level signal supplied to the input terminal IN is not sufficiently low, the base current above described flows through the pull-down resistor RPD, which may push the base potential, and consequently, the emitter potential of the PNP transistor 301, until it is higher than the threshold voltage of the CMOS inverter, and potential of the output terminal OUT may be turned to the ground voltage even when a LOW level signal is supplied to the input terminal IN. This is a problem of the conventional input circuit of FIG. 3.
This problem might be prevented by enlarging the resistance value of the resistance element 308 of FIG. 3. However, when the resistance value of the resistance element 308 is enlarged, it cannot supply sufficient currents to the gates of the pMOS transistor 311 and the nMOS transistor 312, when the input signal is turned from the LOW level to the HIGH level, in order to charge the gate electrodes against their parasitic capacitances for turning the CMOS inverter within a transition time sufficiently short.
Besides the above problem of the current flowing through the base of the PNP transistor 301, there is also a problem of a discrimination level, or an input threshold level, between the HIGH level and the LOW level, in the conventional input circuit of FIG. 3.
The input threshold level, wherefrom the input signal is discriminated to be either at the HIGH level or at the LOW level, is preferably set at a medium point of the VOHMIN (0.4V) and the VOLMAX (2.4V), that is, at 1.4V when the IC is designed according to the TTL interface standard, for obtaining maximum margin against signal distortion because of external noise or against variation of the power supply voltage. This input threshold level can be controlled by changing gate width ratio of the pMOS transistor 311 and the nMOS transistor 312. For example, when the pMOS transistor 311 and the nMOS transistor 312 have the same size, the output terminal OUT becomes at the HIGH level when their gate potential is lower than a half (1.5V) of the power supply voltage and otherwise becomes at the LOW level. When the gate width of the pMOS transistor 311 is made wider than that of the nMOS transistor 312, the output terminal OUT becomes to turn to the LOW level with gate potential higher than 1.5V. On the contrary, the output terminal OUT becomes to turn to the HIGH level with gate potential lower than 1.5V when the gate width of the nMOS transistor 312 is made wider than that of the pMOS transistor 311.
Returning to the input circuit of FIG. 3, the gate potential of the pMOS transistor 311 and the nMOS transistor 312 becomes higher than potential of the input signal supplied to the base of the PNP transistor 301 by base-emitter voltage difference VEBP1 of the PNP transistor 301. Therefore, the input threshold level at the input terminal IN becomes 1.5V (a half of the power supply voltage) -VEBP1, when the pMOS transistor 311 and the nMOS transistor 312 have the same size.
This input threshold level can be shifted to the medium point (1.4V) of the VOHMIN and the VOLMAX, by designing the gate width of the pMOS transistor 311 appropriately wider than the gate width of the nMOS transistor 312. However, when the gate width of the pMOS transistor 311 is made wider, the parasitic capacitance thereof is made larger in proportion to the gate width, which needs longer time for charging, resulting in degradation of the transistion performance. This is another problem of the conventional input circuit of FIG. 3.